1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise gate structures of increased capacitance including a high-k gate dielectric and a metal-containing electrode material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations produced by volume production techniques. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon and metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode, to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a very pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required high capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although the usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same or greater thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
After forming sophisticated gate structures including a high-k dielectric material, however, high temperature treatments may be required which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, thereby offsetting many of the advantages of the high-k dielectric material in combination with the metal-containing electrode material. It is believed that the deterioration of the high-k metal gate may be substantially caused by the interaction of gate stack materials with oxygen and respective oxygen diffusion, which may thus result in a variation of the overall characteristics of the metal gate stack. For example, hafnium oxide and zirconium oxide may exhibit a very high oxidation rate in the presence of oxygen and elevated temperatures, thereby resulting in pronounced modifications of the material characteristics, which may finally lead to significant transistor variability. Consequently, a metal-containing material layer may be formed on the high-k dielectric material to reduce any interaction with the ambient atmosphere, while at the same time providing enhanced performance, since any depletion zone as is typically encountered in polysilicon materials may be avoided. Moreover, upon completing the gate structure, for instance by depositing a standard polysilicon material, a thin silicon nitride spacer may be formed on sidewalls of the gate structure in order to avoid undue exposure of the sensitive materials, i.e., of the high-k dielectric material and metal-containing electrode material, to the ambient atmosphere. For example, a silicon nitride liner having a thickness of one to several nanometers may typically be formed on sidewalls of the gate structure and may be maintained throughout the entire process sequence. Although superior integrity of the sensitive gate stack materials may be accomplished by the metal-containing electrode material and the silicon nitride liner, it nevertheless turns out that a pronounced transistor variability may be observed, for instance in view of threshold variations, which is believed to be caused by interaction of oxygen with the metal-containing electrode material, as will be explained in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 at an early manufacturing stage in forming a sophisticated gate electrode structure according to conventional strategies. As illustrated, the semiconductor device 100 comprises a substrate 101, such as a silicon substrate and the like, above which is formed a semiconductor layer 102, such as a crystalline silicon layer, which may additionally comprise other components, such as germanium and the like. It should be appreciated that a buried insulating material (not shown) may be provided between the substrate 101 and the semiconductor layer 102 if a silicon-on-insulator (SOI) configuration is considered. The portion of the semiconductor layer 102 as shown in FIG. 1a may represent a portion of an active region, i.e., of a semiconductor region having incorporated therein or receiving an appropriate dopant distribution so as to form corresponding PN junctions as required for a transistor to be formed in and above the semiconductor layer 102. For example, the portion of the semiconductor layer 102 shown in FIG. 1a may include a P-type dopant species for forming an N-channel transistor and the like. Moreover, in the manufacturing stage shown, a gate insulation layer 111 is formed on the semiconductor layer 102, wherein the gate insulation layer 111 may typically comprise a high-k dielectric material 111B having an appropriate thickness and permittivity to obtain a desired capacitance equivalent thickness at reduced leakage currents compared to a silicon dioxide based gate dielectric, as previously explained. Furthermore, in view of the superior interface characteristics, a very thin “conventional” dielectric material 111A, for instance in the form of a silicon dioxide material, may be provided, thereby obtaining enhanced stability during subsequent high temperature processes. For example, a thickness of the oxide material 111A may be 0.5-1.0 nm. Furthermore, as discussed above, a metal-containing cap material or electrode material 112 is typically provided on the gate insulation layer 111 so as to reduce any interaction with the ambient atmosphere during the further processing of the device 100. For example, the layer 112 may be provided in the form of titanium nitride, while the high-k dielectric layer 111B may be comprised of hafnium oxide.
Typically, the semiconductor device 100 may be formed on the basis of well-established process techniques involving an oxidation process for forming the base oxide layer 111A, followed by the deposition of the high-k dielectric material 111B by any appropriate deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and the like. Thereafter, the titanium nitride layer 112 may be deposited at moderately low temperatures, for instance by sputter deposition, CVD, PVD and the like, thereby confining the sensitive material 111B. It turns out, however, that the titanium nitride material may itself exhibit an increased affinity to oxygen and may thus show an increased oxidation rate, which is believed to result in significant modifications of the overall gate stack in combination with the subsequent deposition of a polysilicon material. Typically, in many semiconductor processes, many types of oxides, such as silicon dioxide and the like, may be removed prior to a subsequent treatment by performing a cleaning process on the basis of well-established wet chemical etch recipes, such as hydrofluoric acid (HF), which, however, may not be a viable option for forming sophisticated gate electrode structures. For example, in conventional gate patterning processes in which silicon dioxide based gate dielectrics are used, the exposure to the wet chemical etch recipe would result in undue erosion of the gate dielectric material. In this case, an appropriate scheduling of processing substrates may be implemented into the overall process flow, that is, the queue time prior to depositing the polysilicon material on the silicon dioxide based gate dielectric may be appropriately selected so as to maintain the interaction of the gate dielectric material with the ambient atmosphere at an acceptable level.
FIG. 1b schematically illustrates the semiconductor device 100 in the time between the deposition of the titanium nitride layer 112 and the deposition of the polysilicon material, whereby exposing the material 112 to ambient atmosphere and thus oxygen may be present and may interact with the titanium nitride material. However, contrary to conventional silicon dioxide based materials, the titanium nitride layer 112 may exhibit a higher oxidation rate which may thus result in a more pronounced accumulation of oxide which may strongly depend on the scheduling within the semiconductor facility. That is, an appropriate queue time for maintaining device variability at an acceptable level would not be compatible with the scheduling within a complex semiconductor facility, since overall throughput may be significantly reduced or significant additional resources may have to be implemented.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a layer of polysilicon material 113 is formed above the electrode material 112, which is typically accomplished by using well-established low pressure CVD techniques performed at appropriate high temperatures of approximately 600° C. and higher, depending on the desired crystalline structure of the polysilicon material 113. Due to the presence of oxygen, for instance in the form of oxide material of the layer 112, a silicon dioxide material 113A may form during the deposition of the silicon material 113, wherein a thickness and uniformity thereof may significantly depend on the previous process history due to the strong dependence on queue time, as discussed above. Consequently, the layer 113A may form in a highly non-predictable manner, thereby contributing to a significant variation of transistor characteristics, such as threshold voltage, gate resistivity and the like.
FIG. 1d schematically illustrates the semiconductor device 100 in a very advanced manufacturing stage in which a transistor 150 comprises a gate electrode structure 110 including the layers 111A, 111B as a gate insulation layer, the metal-containing electrode material or cap material 112 and the further electrode material 113 in the form of a polysilicon material, wherein the silicon dioxide residues 113A may still be present in a more or less pronounced manner. Furthermore, the gate electrode structure 110 may comprise a metal silicide material 114. Furthermore, a spacer structure 153 may be formed on sidewalls of the gate electrode structure 110 and drain and source regions 152 are formed in the silicon layer 102, wherein metal silicide regions 154 may be formed in a portion of the drain and source regions 152. The components described so far may be formed in accordance with well-established process techniques. As discussed above, due to the presence of the silicon dioxide residues 113A, a significant degree of variability of characteristics of the transistor 150 may be observed, since the additional dielectric material of the residues 113A have an effect on the coupling into a channel region 151, for instance for creating an inversion layer therein, which may thus result in a variability with respect to the threshold voltage of the transistor 150. Additionally, the overall resistivity of the gate electrode structure 110 may also be strongly affected by the layer 113A.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.